This invention is related to the fabrication of multilevel interconnects for integrated circuits and more particularly to the formation of vias for selectively providing electrical interconnections between selected levels of the multilevel structure.
Integrated circuits include a multiplicity of semiconductor devices which are disposed substantially co-planar with respect to one another on a silicon wafer. In order to have a functioning circuit, it is necessary to electrically interconnect the electrical contact regions of these devices. Electrical interconnections, depending on the complexity of the circuit, may require duplication of devices, extensive or complex routing of the interconnects, or both. Such requirements adversely affect circuit densification by utilizing more area than would be necessary if the interconnects were able to be routed without consideration of overlapping metal lines.
It is of course possible to route interconnects over one another without making contact by constructing multilevel integrated circuit devices comprising two or more levels of interconnects separated by a dielectric layer. When constructing such devices, vertical interconnects, sometimes known as vias, are required in order to route signals and signal returns from one level of planar interconnects to another.
As device densification of the integrated circuits becomes greater, aligment of metal to contacts and vias becomes more and more citical. This is due to the fact that greater device density necessarily causes a concomitant increase in contact and interconnect density. Consequently, when it is required to electrically connect a particular contact or interconnect disposed on the substrate to a particular interconnect on the next higher level or to electrically connect two particular interconnects between levels, precise alignment of the vias is mandatory. Misalignment could cause unwanted short circuits between interconnects or between a contact and an interconnect.
In addition to short circuits, a misalignment may also create a marginal electrical contact between the via and the interconnect thereby creating a region of increased current density, a defect which can be potentially fatal to the operation of the circuit. Furthermore, utilizing the prior art technique of via formation which entails deposition of the via material into an aperture etched through the dielectric material separating the interconnect levels, misalignment of the via apertures may cause over etching of the dielectric down to the proximity of the surface of the semiconductor substrate, if not actually into the substrate. Subsequent deposition of the via metal into the aperture could then create defects due to punch through or contamination of the substrate material.
One method of compensating for via misalignment consists of forming pads or nests which are enlargements of the width of the planar interconnects at the approximate via locations. Consequently, the larger the pad or nest, the greater the via misalignment which can be tolerated. Creation of such pads or nests itself has an adverse affect on densification since these enlarged portions of the interconnect preclude closer spacing between interconnects.
Furthermore, placing a metal interconnect line across a contact hole exposing a device contact region, allowance must be made for possible misalignment of the metal line position with respect to the hole, so that the hole will not be uncovered and partially, or even fully in extreme misalignments, exposed to the etches that are used to create the metal interconnect line pattern. This has required in the past that the the metal line width in the vicinity of the hole include a certain fraction of width beyond the electrical requirements of the interconnect line, this fraction being at least equal to the expected maximum misalignment of the line.
This additional width increases the minimum line center to line center spacing that is possible in laying out geometries of the metal interconnection lines. This may be shown by referring to FIG. 13 which depicts metal structures that schematically represent present requirements. As shown in FIG. 13, a "dog bone" structure 702, which is an enlargement of the interconnect line 704, is designed to completely surround the contact region 706 by overlying metal in order to ensure that the contact region 706 is not exposed to etchant used to form the interconnect lines 704. Consequently, the line center to line center distance is equal to W/2+a+d +W/2; where w is the required width of a metal interconnect line, a is the misalignment allowance, and d is the required separation of the metal lines. Consequently, it can be seen that the misalignment allowance, a, increases the necessary line to line spacing.
Accordingly, it is an object of the present invention to provide a method for forming vertical interconnects in multilevel metallization for integrated circuits which are substantially self aligning.
Another object of the present invention is to provide a method of forming vertical interconnects in a multilevel metallization for integrated circuits which permits enhanced densification of devices within the circuit.
It is a further object of the present invention to provide a method for forming vertical interconnects between levels of a multilevel metallization for integrated circuits which enhances reliability of the vertical connection.
It is yet another object of the present invention to provide a method for forming vertical interconnects between levels of a multilevel metallization for integrated circuits while minimizing defects caused by via misalignment.
It is still another object of the present invention to improve misalignment tolerance of metal to contact in integrated circuit structures
It is yet a further object of the present invention to permit closer spacing of interconnect lines and enable increased device density.
It is another object of the present invention to increase the yield of vias and contacts.